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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or oth - erwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad9761 dual 10-bit txdac+ ? with 2 interpolation filters features complete 10-bit, 40 msps dual transmit dac excellent gain and offset matching differential nonlinearity error: 0.5 lsb effective number of bits: 9.5 signal-to-noise and distortion ratio: 59 db spurious-free dynamic range: 71 db 2 interpolation filters 20 msps/channel data rate single supply: 3 v to 5.5 v low power dissipation: 93 mw (3 v supply @ 40 msps) on-chip reference 28-lead ssop functional block diagram a com r eflo i dac fsadj iout a iout b write input select input dcom dvdd cloc k ad9761 2 latc h i r efi o reference comp1 comp2 comp3 bias generator qout a qout b 2 latc h q mu x control avdd dac dat a input s (10 bits) sleep q dac product description the ad9761 is a complete dual-channel, high speed, 10-bit cmos dac. the ad9761 has been developed specifcally for use in wide bandwidth communication applications (e.g., spread spectrum) where digital i and q information is being processed during transmit operations. it integrates two 10-bit, 40 msps dacs, dual 2 interpolation flters, a voltage reference, and digi - tal input interface circuitry. the ad9761 supports a 20 msps per channel input data rate that is then interpolated by 2 up to 40 msps before simultaneously updating each dac. the interleaved i and q input data stream is presented to the digital interface circuitry, which consists of i and q latches as well as some additional control logic. the data is de-interleaved back into its original i and q data. an on-chip state machine ensures the proper pairing of i and q data. the data output from each latch is then processed by a 2 digital interpolation flter that eases the reconstruction flter requirements. the interpo - lated output of each flter serves as the input of their respective 10-bit dac. the dacs utilize a segmented current source architecture com - bined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. each dac provides differential current output, thus supporting single-ended or dif - ferential applications. both dacs are simultaneously updated and provide a nominal full-scale current of 10 ma. also, the full-scale currents between each dac are matched to within 0.07 db (i.e., 0.75%), thus eliminating the need for additional gain calibration circuitry. the ad9761 is manufactured on an advanced low cost cmos process. it operates from a single supply of 3 v to 5.5 v and consumes 200 mw of power. to make the ad9761 complete, it also offers an internal 1.20 v temperature-compensated band gap reference. product highlights 1. dual 10-bit, 40 msps dacs a pair of high performance 40 msps dacs optimized for low distortion performance provide for fexible transmission of i and q information. 2. 2 digital interpolation filters dual matching fir interpolation flters with 62.5 db stop- band rejection precede each dac input, thus reducing the dacs reconstruction flter requirements. 3. low power complete cmos dual dac function operates on a low 200 mw on a single supply from 3 v to 5.5 v. the dac full-scale current can be reduced for lower power opera - tion, and a sleep mode is provided for power reduction during idle periods. 4. on-chip voltage reference the ad9761 includes a 1.20 v temperature-compensated band gap voltage reference. 5. single 10-bit digital input bus the ad9761 features a fexible digital interface that allows each dac to be addressed in a variety of ways including dif - ferent update rates. 6. small package the ad9761 offers the complete integrated function in a compact 28-lead ssop package. 7. product family the ad9761 dual transmit dac has a pair of dual receive adc companion products, the ad9281 (8 bits) and ad9201 (10 bits). rev. c
C2 C ad9761Cspecifications ad9761 C3 C dc specifications (t min to t max , avdd = 5 v, dvdd = 5 v, i outfs = 10 ma, unless otherwise noted.) parameter min typ max unit resolution 10 bits dc accuracy 1 integral nonlinearity error (inl) t a = 25c C1.75 0.5 +1.75 lsb t min to t max C2.75 0.7 +2.75 lsb differential nonlinearity (dnl) t a = 25c C1 0.4 +1.25 lsb t min to t max C1 0.5 +1.75 lsb monotonicity (10-bit) guaranteed over rated specifcation temperature range analog output offset error C0.05 0.025 +0.05 % of fsr offset matching between dacs C0.10 0.05 +0.10 % of fsr gain error (without internal reference) C5.5 1.0 +5.5 % of fsr gain error (with internal reference) C5.5 1.0 +5.5 % of fsr gain matching between dacs C1.0 0.25 +1.0 % of fsr full-scale output current 2 10 ma output compliance range C1.0 +1.25 v output resistance 100 k output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m temperature coefficients unipolar offset drift 0 ppm/c gain drift (without internal reference) 50 ppm/c gain drift (with internal reference) 140 ppm/c gain matching drift (between dacs) 25 ppm/c reference voltage drift 50 ppm/c power supply avdd voltage range 3.0 5.0 5.5 v analog supply current (i avdd ) 26 29 ma dvdd voltage range 2.7 5.0 5.5 v digital supply current at 5 v (i dvdd ) 4 15 18 ma digital supply current at 3 v (i dvdd ) 4 5 ma nominal power dissipation 5 avdd and dvdd at 3 v 93 mw avdd and dvdd at 5 v 200 250 mw power supply rejection ratio (psrr)Cavdd C0.25 +0.25 % of fsr/v power supply rejection ratio (psrr)Cdvdd C0.02 +0.02 % of fsr/v operating range C40 +85 c notes 1 measured at iouta and qouta, driving a virtual ground. 2 nominal full-scale current, i outfs , is 16 the i ref current. 3 use an external amplifer to drive any external load. 4 measured at f clock = 40 msps and f out = 1 mhz. 5 measured as unbuffered voltage output into 50 r load at iouta, ioutb, qouta, and qoutb; f clock = 40 msps and f out = 8 mhz. specifcations subject to change without notice. rev. c rev. c
C2 C ad9761Cspecifications ad9761 C3 C dynamic specifications (t min to t max , avdd = 5 v, dvdd = 5 v, i outfs = 10 ma, differential transformer coupled output, 50 doubly terminated, unless otherwise noted.) digital specifications (t min to t max , avdd = 5 v, dvdd = 5 v, i outfs = 10 ma unless otherwise noted.) parameter min typ max unit dynamic performance maximum output update rate 40 msps output settling time (t st to 0.025%) 35 ns output propagation delay (t pd ) 55 input clock cycles glitch impulse 5 pv-s output rise time (10% to 90%) 2.5 ns output fall time (10% to 90%) 2.5 ns ac linearity to nyquist signal-to-noise and distortion (sinad) f out = 1 mhz; clock = 40 msps 56 59 db effective number of bits (enobs) 9.0 9.5 bits total harmonic distortion (thd) f out = 1 mhz; clock = 40 msps t a = 25c C68 C58 db t min to t max C67 C53 db spurious-free dynamic range (sfdr) f out = 1 mhz; clock = 40 msps; 10 mhz span 59 68 db channel isolation f out = 8 mhz; clock = 40 msps; 10 mhz span 90 dbc specifcations subject to change without notice. parameter min typ max unit digital inputs logic 1 voltage @ dvdd = 5 v 3.5 5 v logic 1 voltage @ dvdd = 3 v 2.4 3 v logic 0 voltage @ dvdd = 5 v 0 1.3 v logic 0 voltage @ dvdd = 3 v 0 0.9 v logic 1 current C10 +10 a logic 0 current C10 +10 a input capacitance 5 pf input setup time (t s ) 3 ns input hold time (t h ) 2 ns clock high 5 ns clock low 5 ns invalid clock/write window (t cinv ) * 1 5 ns * t cinv is an invalid window of 4 ns duration beginning 1 ns after the rising edge of write in which the rising edge of clock must not occur. specifcations subject to change without notice. i data q data t cinv db9Cdb0 dac inputs select write clock t s t h note: write and clock can be tied together. for typical examples, refer to digital inputs and interleaved interface consideration section. figure 1. timing diagram rev. c rev. c
ad9761 C4 C ad9761 C5 C digital filter specifications (t min to t max , avdd = 2.7 v to 5.5 v, dvdd = 2.7 v to 5.5 v, i outfs = 10 ma, unless otherwise noted.) parameter min typ max unit maximum input clock rate (f clock ) 40 msps digital filter characteristics pass bandwidth 1 : 0.005 db 0.2010 f out /f clock pass bandwidth: 0.01 db 0.2025 f out /f clock pass bandwidth: 0.1 db 0.2105 f out /f clock pass bandwidth: C3 db 0.239 f out /f clock linear phase (fir implementation) stop-band rejection: 0.3 f clock to 0.7 f clock C62.5 db group delay 2 32 input clock cycles impulse response duration 3 C40 db 28 input clock cycles C60 db 40 input clock cycles notes 1 excludes sinx/x characteristic of dac. 2 defned as the number of data clock cycles between impulse input and peak of output response. 3 55 input clock periods from input to i dac, 56 to q dac. propagation delay is delay from data input to dac update. specifcations subject to change without notice. frequency response (dc to f clock /2) output (dbfs) 0 C20 C120 0 0.5 0.1 0.2 0.3 0.4 C40 C60 C80 C100 figure 2a. fir filter frequency response time (samples) 1 0 0 4 0 5 10 15 20 25 30 3 5 0.9 0.6 0.4 0.2 0.1 0.8 0.7 0.5 0.3 C0.1 C0.2 C0.3 normalized output figure 2b. fir filter impulse response table i. integer filter coeffcients for 43-tap half-band fir filter lower coeffcient upper coeffcient integer value h(1) h(43) 1 h(2) h(42) 0 h(3) h(41) C3 h(4) h(40) 0 h(5) h(39) 8 h(6) h(38) 0 h(7) h(37) C16 h(8) h(36) 0 h(9) h(35) 29 h(10) h(34) 0 h(11) h(33) C50 h(12) h(32) 0 h(13) h(31) 81 h(14) h(30) 0 h(15) h(29) C131 h(16) h(28) 0 h(17) h(27) 216 h(18) h(26) 0 h(19) h(25) C400 h(20) h(24) 0 h(21) h(23) 1264 h(22) 1998 rev. c rev. c
ad9761 C4 C ad9761 C5 C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9761 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide package package model description option ad9761ars 28-lead shrink small outline (ssop) rs-28 AD9761ARSRL 28-lead shrink small outline (ssop) rs-28 ad9761-eb evaluation board thermal characteristics thermal resistance 28-lead ssop q ja = 109c/w comp1 i dac fsadj iouta ioutb write select comp2 avdd avss ad9761 2x latch i reflo q dac qouta qoutb 2x latch q mux control comp3 db9Cdb0 sleep clock refio 100 50 20pf 50 20pf digital data tektronix awg-2021 clock out marker 1 retimed clock output * le croy 9210 pulse generator * awg2021 clock retimed such that digital data transitions on falling edge of 50% duty cycle clock. mini-circuits t1-1 t r set 2k 0.1 f to hp3589a spectrum/networ k analyzer 50 input 100 50 20pf 50 20pf mini-circuits t1-1 t to hp3589a spectrum/networ k analyzer 50 input 0.1 f 0.1 f 0.1 f dvdd dcom 2.7v to 5.5v 3v to 5.5v figure 3. basic ac characterization test setup absolute maximum ratings * with parameter respect to min max unit avdd acom C0.3 +6.5 v dvdd dcom C0.3 +6.5 v acom dcom C0.3 +0.3 v avdd dvdd C6.5 +6.5 v clock, write dcom C0.3 dvdd + 0.3 v select, sleep dcom C0.3 dvdd + 0.3 v digital inputs dcom C0.3 dvdd + 0.3 v iouta, ioutb acom C1.0 avdd + 0.3 v qouta, qoutb acom C1.0 avdd + 0.3 v comp1, comp2 acom C0.3 avdd + 0.3 v comp3 acom C0.3 avdd + 0.3 v refio, fsadj acom C0.3 avdd + 0.3 v reflo acom C0.3 +0.3 v junction temperature 150 c storage temperature C65 +150 c lead temperature (10 sec) 300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. rev. c rev. c
ad9761 C6 C ad9761 C7 C pin function descriptions pin no. mnemonic description 1 db9 most signifcant data bit (msb). 2C9 db8Cdb1 data bits 1C8. 10 db0 least signifcant data bit (lsb). 11 clock clock input. both dacs outputs updated on positive edge of clock and digital flters read respective input registers. 12 write write input. dac input registers latched on positive edge of write. 13 select select input. select high routes input data to i dac; select low routes data to q dac. 14 dvdd digital supply voltage (2.7 v to 5.5 v). 15 dcom digital common. 16 comp3 internal bias node for switch driver circuitry. decouple to acom with 0.1 f capacitor. 17 qouta q dac current output. full-scale current when all data bits are 1s. 18 qoutb q dac complementary current output. full-scale current when all data bits are 0s. 19 reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 20 refio reference input/output. serves as reference input when internal reference disabled. serves as 1.2 v reference output when internal reference activated. requires 0.1 f capacitor to acom when internal reference activated. 21 fsadj full-scale current output adjust. resistance to acom sets full-scale output current. 22 comp2 bandwidth/noise reduction node. add 0.1 f to avdd for optimum performance. 23 avdd analog supply voltage (3 v to 5.5 v). 24 acom analog common. 25 ioutb i dac complementary current output. full-scale current when all data bits are 0s. 26 iouta i dac current output. full-scale current when all data bits are 1s. 27 comp1 internal bias node for switch driver circuitry. decouple to agnd with 0.1 f capacitor. 28 reset/sleep power-down control input if asserted for four clock cycles or longer. reset control input if asserted for less than four clock cycles. active high. connect to dcom if not used. refer to reset/ sleep mode operation section. pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9761 (msb) db9 ioutb iouta comp1 reset/sleep db8 db7 db6 comp2 avdd aco m db5 db4 db3 db2 db1 (lsb) db0 reflo refio fsadj clock write select dvdd qoutb dco m comp3 qouta rev. c rev. c
ad9761 C6 C ad9761 C7 C definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defned as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specifed as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specifed voltages. settling time the time required for the output to reach and remain within a specifed error band about its fnal value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantifed by a glitch impulse. it is specifed as the net area of the glitch in pv-s. channel isolation channel isolation is a measure of the level of crosstalk between channels. it is measured by producing a full-scale 8 mhz signal output for one channel and measuring the leakage into the other channel. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specifed bandwidth. total harmonic distortion thd is the ratio of the sum of the rms value of the frst six harmonic components to the rms value of the measured output signal. it is expressed as a percentage or in decibels (db). signal-to-noise and distortion (s/n+d, sinad) ratio s/n+d is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, n = ( sinad C 1.76)/6.02 it is possible to get a measure of performance expressed as n , the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. pass band frequency band in which any input applied therein passes unattenuated to the dac output. stop-band rejection the amount of attenuation of a frequency outside the pass band applied to the dac, relative to a full-scale signal applied at the dac input within the pass band. group delay number of input clocks between an impulse applied at the device input and peak dac output current. impulse response response of the device to an impulse applied to the input. rev. c rev. c
C8 C ad9761typical performance characteristics ad9761 C9 C typical ac characterization curves @ 5 v supplies (avdd = 5 v, dvdd = 5 v, 50 doubly terminated load, t a = 25 c, f clock = 40 msps, unless otherwise noted, worst of i or q output performance shown.) 0 C10 C20 C30 C40 C50 C70 C60 C80 C90 start: 0hz stop: 40mhz 10db (div ) C100 tpc 1. single-tone sfdr (dc to 2 f data , f clock = 2 f data ) f out (mhz) db 75 70 60 65 2.0 4.0 10.0 s/e 0dbfs diff 0 dbfs s/e C6dbfs diff C6dbfs 55 50 0 6.0 8.0 tpc 4. out-of-band sfdr vs. f out (f data /2 to 3/2 f data ) f out (mhz) db 80 70 sfdr @ 10ma 65 2 75 60 55 0 sinad @ 10ma sfdr @ 5ma sinad @ 5ma sfdr @ 2.5ma sinad @ 2.5ma 4 6 8 1 0 tpc 7. sinad/sfdr vs. i outfs (dc to f data /2, differential output) f ou t (mhz) db 65 60 50 55 0 2.0 10.0 4.0 6.0 8.0 10.50 9.67 8.01 8.84 enob s/e 0dbf s diff 0dbf s s/e C6dbf s diff C6dbf s tpc 2. sinad (enobs) vs. f out (dc to f data /2) a out (dbfs) db 80 75 60 65 C25 C20 C5 sfdr @ 40msps 55 50 C30 C15 C10 sinad @ 40msps sfdr @ 20msps sinad @ 20msps sfdr @ 10msps sinad @ 10msps 70 45 40 35 C0 tpc 5. sinad vs. a out (dc to f data /2, differential output) f out (mhz) db 80 70 sfdr @ 10ma 65 2 75 60 55 0 sinad @ 10ma sfdr @ 5ma sinad @ 5ma sfdr @ 2.5ma sinad @ 2.5ma 4 6 8 1 0 tpc 8. sinad/sfdr vs. i outfs (dc to f data /2, single-ended output) f out (mhz) db 80 75 65 70 0 5.0 10.0 s/e 0dbfs diff 0dbfs s/e C6dbfs diff C6dbfs tpc 3. sfdr vs. f out (dc to f data /2) a out (dbfs) db 80 75 60 65 C25 C20 C5 sfdr @ 40msps 55 50 C30 C15 C10 sinad @ 40msps sfdr @ 20msps sinad @ 20msps sfdr @ 10msps sinad @ 10msps 70 45 40 35 0 tpc 6. sinad vs. a out (dc to f data /2, single-ended output) C45 C65 C55 C75 C85 start: 0hz stop: 20mhz 10db (div) C105 C95 tpc 9. wideband spread- spectrum spectral plot (dc to f data ) rev. c rev. c
C8 C ad9761typical performance characteristics ad9761 C9 C typical ac characterization curves @ 3 v supplies (avdd = 3 v, dvdd = 3 v, 50 doubly terminated load, t a = 25 c, f clock = 10 msps, unless otherwise noted, worst of i or q output performance shown.) 0 C10 C20 C30 C40 C50 C70 C60 C80 C90 start: 0h z stop: 10mhz 10db (div ) tpc 10. single-tone sfdr (dc to 2 f data , f clock = 2 f data ) f out (mhz) db 75 70 60 65 0 0.5 2.5 1.0 1.5 2.0 s/e 0dbfs diff 0dbfs s/e C6dbfs diff C6dbfs 80 tpc 13. out-of-band sfdr vs. f out (f data /2 to 3/2f data ) f out (mhz) db 80 70 sfdr @ 10ma 65 2 75 60 55 0 sinad @ 10ma sfdr @ 5ma sinad @ 5ma sfdr @ 2.5ma sinad @ 2.5ma 4 6 8 1 0 tpc 16. sinad/sfdr vs. i outfs (dc to f data /2, differential output) f out (mhz) db 65 60 50 55 0 0.5 2.5 1.0 1.5 2.0 10.50 9.67 8.01 8.84 enob s/e 0dbfs diff 0dbfs s/e C6dbfs diff C6dbfs tpc 11. sinad (enobs) vs. f out (dc to f data /2) a ou t (dbfs) db 75 70 60 65 C30 C25 C5 C20 C15 C10 sfdr @ 40msps 80 sfdr @ 20msps sfdr @ 10msps sinad @ 40msps sinad @ 20msps sinad @ 10msps 55 50 45 40 35 0 tpc 14. sinad vs. a out (dc to f data /2, differential output) sfdr @ 10m a f ou t (mhz) db 80 70 65 2 75 60 55 0 sinad @ 10m a sfdr @ 5m a sinad @ 5m a sfdr @ 2.5m a sinad @ 2.5m a 4 6 8 1 0 tpc 17. sinad/sfdr vs. i outfs (dc to f data /2, single-ended output) f out (mhz) db 75 70 60 65 0 0.5 2.5 1.0 1.5 2.0 s/e 0dbfs diff 0dbfs s/e C6dbfs diff C6dbfs 80 85 tpc 12. sfdr vs. f out (dc to f data /2) a out (dbfs) db 70 65 55 60 C30 C25 C5 C20 C15 C10 sfdr @ 40msps 75 sfdr @ 20msps sfdr @ 10msps sinad @ 20msps sinad @ 10msps 50 45 40 35 30 0 sinad @ 40msps tpc 15. sinad vs. a out (dc to f data /2, single-ended output) 0 C10 C20 C30 C40 C50 C70 C60 C80 start: 0h z stop: 10mhz 10db (div ) tpc 18. narrow-band spread- spectrum spectral plot (dc to f data ) rev. c rev. c
ad9761 C1 0 C ad9761 C1 1 C functional description figure 4 shows a simplifed block diagram of the ad9761. the ad9761 is a complete dual-channel, high speed, 10-bit cmos dac capable of operating up to a 40 mhz clock rate. it has been optimized for the transmit section of wideband communica - tion systems employing i and q modulation schemes. excellent matching characteristics between channels reduce the need for any external calibration circuitry. dual matching 2 interpola - tion flters included in the i and q data path simplify any post band-limiting flter requirements. the ad9761 interfaces with a single 10-bit digital input bus that supports interleaved i and q input data. a com r eflo i dac fsadj iout a iout b write input select input dcom dvdd cloc k ad9761 2 latc h i r efi o reference comp1 comp2 comp3 bias generator qout a qout b 2 latc h q mu x control avdd dac dat a input s (10 bits) sleep q dac figure 4. dual dac functional block diagram referring to figure 4, the ad9761 consists of an analog sec - tion and a digital section. the analog section includes matched i and q 10-bit dacs, a 1.20 v band gap voltage reference, and a reference control amplifer. the digital section includes two 2 interpolation flters, segment decoding logic, and some additional digital input interface circuitry. the analog and digital sections of the ad9761 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently. the digital supply can operate over a 2.7 v to 5.5 v range, allowing it to accommodate ttl as well as 3.3 v and 5 v cmos logic families. the analog supply must be restricted from 3.0 v to 5.5 v to maintain opti - mum performance. each dac consists of a large pmos current source array capable of providing up to 10 ma of full-scale current, i outfs . each array is divided into 15 equal currents that make up the four most signif - cant bits (msbs). the next four bits or middle bits consist of 15 equal current sources whose values are 1/16 of an msb current source. the remaining lsbs are binary weighted fractions of the middle bits current sources. all of these current sources are switched to one of two output nodes (i.e., iouta or ioutb) via pmos differential current switches. the full-scale output current, i outfs , of each dac is regulated from the same voltage reference and control amplifer, thus ensuring excellent gain matching and drift characteristics between dacs. i outfs can be set from 1 ma to 10 ma via an external resistor, r set . the external resistor in combination with both the reference control amplifer and voltage reference, v refio , sets the reference current, i ref , which is mirrored over to the segmented current sources with the proper scaling factor. i outfs is exactly 16 times the value of i ref . the i and q dacs are simultaneously updated on the rising edge of clock with digital data from their respective 2 digital interpolation flters. the 2 interpolation flters essen - tially multiply the input data rate of each dac by a factor of 2, relative to its original input data rate, while simultaneously reducing the magnitude of the frst image associated with the dacs original input data rate. since the ad9761 supports a single 10-bit digital bus with interleaved i and q input data, the original i and q input data rate before interpolation is one-half the clock rate. after interpolation, the data rate into each i and q dac becomes equal to the clock rate. the benefts of an interpolation flter are illustrated in figure 5, which shows an example of the frequency and time domain rep - resentation of a discrete time sine wave signal before and after it is applied to a digital interpolation flter. images of the sine wave signal appear around multiples of the dacs input data rate as predicted by the sampling theory. these undesirable images will also appear at the output of a reconstruction dac, although modifed by the dacs sin(x)/(x) response. in many band-limited applications, these images must be suppressed by an analog flter following the dac. the complexity of this ana - fundamenta l 1 f clock fundamenta l digital filte r suppressed ol d 1 st imag e ne w 1st imag e f cloc k 1 st imag e 2 f clock f cloc k f cloc k 2 f cloc k dacs sin(x) x time domain frequency domain 2 interpolation filte r input data latc h dac f cloc k f cloc k 2 f cloc k 2 f cloc k 2 2 figure 5. time and frequency domain example of digital interpolation filter rev. c rev. c
ad9761 C1 0 C ad9761 C1 1 C log flter is typically determined by the proximity of the desired fundamental to the frst image and the required amount of image suppression. referring to figure 5, the new frst image associated with the dacs higher data rate after interpolation is pushed out fur - ther relative to the input signal. the old frst image associated with the lower dac data rate before interpolation is suppressed by the digital flter. as a result, the transition band for the analog reconstruction flter is increased, thus reducing the complexity of the analog flter. the digital interpolation flters for i and q paths are identi - cal 43-tap half-band symmetric fir flters. each flter receives de-interleaved i or q data from the digital input interface. the input clock signal is internally divided by 2 to generate the flter clock. the flters are implemented with two parallel paths running at the flter clock rate. the output from each path is selected on opposite phases of the flter clock, thus producing interpolated fltered output data at the input clock rate. the frequency response and impulse response of these flters are shown in figures 2a and 2b. table i lists the idealized flter coeffcients that correspond to the flters impulse response. the digital section of the ad9761 also includes an input interface section designed to support interleaved i and q input data from a single 10-bit bus. this section de-interleaves the i and q input data while ensuring its proper pairing for the 2 interpolation flters. a reset/sleep input serves a dual function by providing a reset function for this section as well as providing power-down functionality. refer to the digital inputs and interleaved interface considerations and reset/sleep mode operation sections for a more detailed discussion. dac transfer function each i and q dac provides complementary current output pins: iout(a/b) and qout(a/b), respectively. note that qouta and qoutb operate identically to iouta and ioutb. iouta will provide a near full-scale current output, i outfs , when all bits are high (i.e., dac code = 1023), while ioutb, the complementary output, provides no current. the current outputs of iouta and ioutb are a function of both the input code and i outfs and can be expressed as i dac code / i outa outfs = ( ) 1024 (1) i C dac code i outb outfs = ( ) 1023 1024 / (2) where: dac code = 0 to 1023 (i.e., decimal representation). as previously mentioned, i outfs is a function of the reference current, i ref , which is nominally set by a reference, v refio , and external resistor, r set . it can be expressed as i i outfs ref = 16 (3) where: i v r ref refio set = / (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, iouta and ioutb should be directly connected to matching resistive loads, r load , which are tied to analog common, acom. note that r load represents the equivalent load resistance seen by iouta or ioutb. the single-ended voltage output appearing at iouta and ioutb pins is simply v i r iouta outa load = (5) v i r ioutb outb load = (6) note that the full-scale value of v iouta and v ioutb should not exceed the specifed output compliance range to maintain speci - fed distortion and linearity performance. the differential voltage, v idiff , appearing across iouta and ioutb is v i i r idiff iouta ioutb load = ( ) C (7) substituting the values of i iouta , i ioutb , and i ref , v idiff can be expressed as v dac code C r r v idiff load set refio = ( ) ) { } ( ) 2 1023 102 4 16 / / (8) these last two equations highlight some of the advantages of operating the ad9761 differentially. first, differential opera - tion will help cancel common-mode error sources associated with i iouta and i ioutb , such as noise and distortion. second, the differential code-dependent current and subsequent volt - age, v idiff , is twice the value of the single-ended voltage output (i.e., v iouta or v ioutb ), thus providing twice the signal power to the load. reference operation the ad9761 contains an internal 1.20 v band gap reference that can be easily disabled and overridden by an external reference. refio serves as either an input or output depending on whether the internal or an external reference is selected. if reflo is tied to acom as shown in figure 6, the internal reference is activated and refio provides a 1.20 v output. in this case, the internal ref - erence must be fltered externally with a ceramic chip capacitor of 0.1 f or greater from refio to reflo. also, refio should be buffered with an external amplifer having a low input bias current (i.e., <1 a) if any additional loading is required. 50pf current source array +1.2v ref refi o fsadj reflo comp2 avdd 0.1 f r set 2k 0.1 f optional external ref buffer for additional loads compensation capacitor require d ad9761 figure 6. internal reference confguration the internal reference can also be disabled by connecting reflo to avdd. in this case, an external reference may then be applied to refio as shown in figure 7. the external reference may provide either a fxed reference voltage to enhance accura - cy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required since the internal reference is disabled and the high input impedance (i.e., 1 m ) of refio minimizes any loading of the external reference . rev. c rev. c
ad9761 C1 2 C ad9761 C1 3 C 50pf current source array +1.2v ref refi o fsadj reflo comp2 avdd i ref = v ref /r set avdd r set ext. v ref avdd 0.1 f ad9761 + C figure 7. external reference confguration reference control amplifier the ad9761 also contains an internal control amplifer that is used to simultaneously regulate both dacs full-scale out put current, i outfs . since the i and q i outfs are derived from the same voltage reference and control circuitry, ex cellent gain matching is ensured. the control amplifer is confgured as a v-i converter as shown in figure 7 such that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is cop ied over to the segmented current sources with the proper scal ing factor to set i outfs as stated in equation 3. the control amplifer allows a wide (10:1) adjustment span of i outfs over a 1 ma to 10 ma range by setting i ref be tween 62.5 a and 625 a. the wide adjustment span of i outfs provides several application benefts. the frst beneft relates directly to the power dissipation of the ad9761s analog supply, avdd, which is proportional to i outfs (refer to the power dissipation section). the second beneft relates to the 20 db adjustment span, which may be useful for sys tem gain control purposes. optimum noise and dynamic performance for the ad9761 is obtained with a 0.1 f external capacitor installed be tween comp2 and avdd. the bandwidth of the reference control amplifer is limited to approximately 5 khz with a 0.1 f capacitor installed. since the C3 db bandwidth corresponds to the dominant pole and therefore its dominant time con - stant, the settling time of the control amplifer to a stepped refer ence input response can be easily determined. note that the output of the control amplifer, comp2, is internally compensated via a 50 pf capacitor, thus ensuring its stabil - ity if no external capacitor is added. depending on the requirements of the application, i ref can be adjusted by varying either r set , or, in the external reference mode, by varying the refio voltage. i ref can be varied for a fxed r set by disabling the internal reference and varying the voltage of refio over its compliance range of 1.25 v to 0.10 v. refio can be driven by a single-supply amplifer or dac, thus allowing i ref to be varied for a fxed r set . since the input impedance of refio is approximately 1 m , a simple, low cost r-2r ladder dac confgured in the voltage mode topology may be used to control the gain. this circuit is shown in figure 8 using the ad7524 and an external 1.2 v reference, the ad1580. analog outputs as previously stated, both the i and q dacs produce two complementary current outputs that may be confgured for single-ended or differential operation. i iouta and i ioutb can be converted into complementary single-ended voltage outputs, v iouta and v ioutb , via a load resistor, r load , as described in the dac transfer function section by equations 5 through 8. the differential voltage, v idiff , existing between v iouta and v ioutb , can also be converted to a single-ended voltage via a transformer or differential amplifer confguration. figure 9 shows an equivalent circuit of the ad9761s i (or q) dac output. it consists of a parallel array of pmos current sources in which each current source is switched to either iouta or ioutb via a differential pmos switch. as a re sult, the equivalent output impedance of iouta and ioutb remains quite high (i.e., >100 k and 5 pf). ad9761 avdd r loa d r load iouta ioutb figure 9. equivalent circuit of the ad9761 dac output iouta and ioutb have a negative and positive voltage compliance range that must be adhered to achieve optimum performance. the negative output compliance range of C1 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a breakdown of the output stage. 50pf current source array +1.2v ref refi o fsadj reflo comp2 avdd avdd ad1580 1.2v optional band limiting capacitor i ref = v ref /r set avdd r set 0.1v to 1.2v r fb v dd out1 out2 agnd v ref ad7524 db7Cdb0 + C ad9761 figure 8. single-supply gain control circuit rev. c rev. c
ad9761 C1 2 C ad9761 C1 3 C the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.25 v for an i outfs = 10 ma to 1.00 v for an i outfs = 2 ma. applications requiring the ad9761s output (i.e., v outa and/or v outb ) to extend to its output compliance range should size r load accordingly. operation beyond this compliance range will adversely affect the ad9761s linear ity performance and subsequently degrade its distortion per for - mance. note that the optimum distortion performance of the ad9761 is obtained by restricting its output(s) as seen at iout(a/b) and qout(a/b) to within 0.5 v. digital inputs and interleaved interface considerations the ad9761 digital interface consists of 10 data input pins, a clock input pin, and three control pins. it is designed to support a clock rate up to 40 msps. the 10-bit parallel data inputs follow standard positive binary coding, where db9 is the most signifcant bit (msb) and db0 is the least sig nifcant bit (lsb). iouta (or qouta) produces a full-scale out put current when all data bits are at logic 1. ioutb (or qoutb) produces a complementary output, with the full-scale current split between the two outputs as a function of the input code. state machine i and q data clock select reset/sleep write q data clock 2 i data i input register i filter register q input register q input register figure 10. block diagram of digital interface the ad9761 interfaces with a single 10-bit digital input bus that supports interleaved i and q input data. figure 10 shows a simplifed block diagram of the digital interface circuitry consisting of two banks of edge triggered registers, two multiplexers, and a state machine. interleaved i and q input data is presented at the data input bus, where it is then latched into the selected i or q input register on the rising edge of the write input. the output of these input registers is transferred in pairs to their respective interpola - tor flters register after each q write on the rising edge of the clock input (refer to timing diagram in figure 1). a state machine ensures the proper pairing of i and q in put data to the interpolation flters inputs. the select signal at the time of the rising edge of the write signal determines which input register latches the input data. if select is high around the rising edge of write, the data is latched into the i register of the ad9761. if select is low around the rising edge of write, the data is latched into the q register of the ad9761. if select is kept in one state while data is repeatedly writing to the ad9761, the data will be written into the selected flter register at half the input data rate since the data is always assumed to be interleaved. the state machine controls the generation of the divided clock and thus pairing of i and q data inputs. after the ad9761 is reset, the state machine keeps track of the paired i and q data. the state transition diagram is shown in fig - ure 11, in which all states are defned. a transition in state occurs upon the rising edge of clock and is a function of the current state as well as status of select, write, and sleep. the state machine is reset on the frst rising clock edge while reset remains high. upon reset returning low, a state transition will occur on the frst rising edge of clock. the most recent i and q data samples are transferred to the correct interpolation flter only upon entering state filter data. note that it is possible to ensure proper pairing of i and q data inputs without issuing reset high. this may be accomplished by writing two or more successive q data inputs followed by a clock. in this case, the state machine will ad vance to either the reset or filter data state. the state machine will advance to the one-i state upon writing i data followed by a clock. one, i reset filte r dat a i or q or n n i = write and select followed by a clock q = write and selec t followed by a clock n = clock only, no writ e i i q q or n figure 11. state transition diagram of ad9761 digital interface an example helps illustrate the digital timing and control requirements to ensure proper pairing of i and q data. in this example, the ad9761 is assumed to interface with a host processor on a dedicated data bus and the state machine is reset by asserting a logic level 1 to the reset/sleep input for a duration of one clock cycle. in the timing dia gram shown in figure 12, write and clock are tied together while select is updated at the same instance as data. since select is high upon reset returning low, i data is latched into the i input register on the frst rising write. on the next rising write edge, the q data is latched into its input register and the outputs of both input registers are latched into their respective i and q filter registers. the sequence of events is repeated on the next rising write edge with the new i data being latched into the i input register. the digital inputs are cmos compatible with logic thresholds, v threshold , set to approximately half the digital positive supply (dvdd) or v threshold = dvdd /2 (20%). the internal digital circuitry of the ad9761 is capable of operating over a digital supply range of 2.7 v to 5.5 v. as a rev. c rev. c
ad9761 C1 4 C ad9761 C1 5 C result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage, v oh(max) , of the ttl drivers. a dvdd of 3 v to 3.3 v will typically ensure proper compatibility of most ttl logic families. figure 13 shows the equivalent digital input circuit for the data, sleep, and clock inputs. reset data select clock/write i 0 q 0 i 1 q 1 figure 12. timing diagram dvdd digital input figure 13. equivalent digital input since the ad9761 is capable of being updated up to 40 msps, the quality of the clock and data input signals are important in achieving the optimum performance. the drivers of the digital data interface circuitry should be specifed to meet the minimum setup and hold times of the ad9761 as well as its required min/max input logic level thresholds. the external clock driver circuitry should provide the ad9761 with a low jitter clock input meeting the min/max logic levels while providing fast edges. fast clock edges will help minimize any jitter that can manifest itself as phase noise on a reconstructed waveform. digital signal paths should be kept short, and run lengths matched to avoid propagation delay mismatch. the inser - tion of a low value resistor network (i.e., 20 to 100 ) between the ad9761 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs, which contributes to data feedthrough. operating the ad9761 with reduced logic swings and a corresponding digital supply (dvdd) will also reduce data feedthrough. reset/sleep mode operation the reset/sleep input can be used either to power down the ad9761 or reset its internal digital interface logic. if the reset/sleep input is asserted for greater than one clock cycle but under four clock cycles by applying a logic 1, the internal state machine will be reset. if the reset/sleep input is asserted for four clock cycles or longer, the power-down func - tion of the ad9761 will be initiated. the power-down function turns off the output current and reduces the supply current to less than 9 ma over the specifed supply range of 3 v to 5.5 v and temperature range . the power-up and power-down characteristics of the ad9761 are dependent upon the value of the compensation capacitor connected to comp1 and comp3. with a nominal value of 0.1 f, the ad9761 takes less than 5 s to power down and approximately 3.25 ms to power back up. power dissipation the power dissipation of the ad9761 is dependent on several factors, including 1. avdd and dvdd, the power supply voltages. 2. i outfs , the full-scale current output. 3. f clock , the update rate. 4. the reconstructed digital input waveform. the power dissipation is directly proportional to the ana log supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs , as shown in fig - ure 14, and is insensitive to f clock . i outfs (ma) 30 0 1 1 0 2 3 4 5 6 7 8 9 25 20 15 10 5 i avdd (ma) figure 14. i avdd vs. i outfs conversely, i dvdd is dependent on both the digital input waveform, f clock , and digital supply, dvdd. figures 15 and 16 show i dvdd as a function of a full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 5 v and dvdd = 3 v, respectively . 5msps ratio (f ou t /f cl k ) 40 30 0.05 0.15 40msps 20 0 0.10 20msps 10msps 10 0 i dvdd (ma ) 0.20 50 60 70 2.5msps figure 15. i dvdd vs. ratio @ dvdd = 5 v rev. c rev. c
ad9761 C1 4 C ad9761 C1 5 C 5msps ratio (f ou t /f cl k ) 40 30 0.05 0.15 40msps 20 0 0.10 20msps 10msps 10 0 i dvdd (ma ) 0.20 2.5msps 5 35 25 15 figure 16. i dvdd vs. ratio @ dvdd = 3 v applying the ad9761 output confgurations the following sections illustrate some typical output confgu - rations for the ad9761. unless otherwise noted, it is assumed that i outfs is set to a nominal 10 ma. for applications requir - ing the optimum dynamic performance, a differential output confguration is suggested. a differential output confguration may consist of either an rf transformer or a differential op amp confguration. the transformer confguration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. the differential op amp confguration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output volt age will result if iouta and/or ioutb is connected to an appropriately sized load resistor, r load , referred to acom. this confguration may be more suitable for a single-sup ply system requiring a dc-coupled, ground referred output volt - age. alternatively, an amplifer could be confgured as an i-v converter, thus converting i outa or i outb into a negative unipolar voltage. this confguration provides the best dc linearity since iouta or ioutb is maintained at a virtual ground. differential coupling using a transformer an rf transformer can be used to perform a differential- to-single-ended signal conversion as shown in figure 17. a differentially coupled transformer output provides the op timum distortion performance for output signals whose spectral content lies within the transformers pass band. an rf transformer such as the mini-circuits t1-1t provides excellent rejection of common-mode distortion (i.e., even-or der harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different imped ance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. optional r diff r l oad mini-circuits t1-1t iouta ioutb ad9761 figure 17. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc cur rent path for both i outa and i outb . the complementary voltages appearing at iouta and ioutb (i.e., v outa and v outb ) swing symmetrically around acom and should be main tained with the specifed output compliance range of the ad9761. a differential resistor, r diff , may be inserted in applica tions in which the output of the transformer is connected to the load, r load , via a passive reconstruction flter or cable requiring double termination. r diff is determined by the transformers impedance ratio and provides the proper source termination, which results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential to single-ended conversion as shown in figure 18. the ad9761 is confgured with two equal load resistors, r load , of 50 . the differential voltage developed across iouta and ioutb is converted to a single-ended signal via the differential op amp confguration. an optional capacitor can be installed across iouta and ioutb forming a real pole in a low-pass flter. the addition of this capacitor also enhances the op amps distortion performance by prevent - ing the dacs high slewing output from overloading the op amps input. c opt 200 500 iouta ioutb ad9761 r load 50 200 ad8042 500 r load 50 figure 18. dc differential coupling using an op amp the common-mode rejection of this confguration is typi cally determined by the resistor matching. in this circuit, the differential op amp circuit using the ad8042 is confgured to provide some additional signal gain. the op amp must operate from a dual supply since its output is approxi mately 1.0 v. a high speed amplifer capable of preserving the differential performance of the ad9761 while meeting other system level objectives (i.e., cost, power) should be select ed. the op amps differential gain, gain setting resistor val ues, and full-scale output swing capabilities should all be con sid - ered when optimizing this circuit. rev. c rev. c
ad9761 C1 6 C ad9761 C1 7 C the differential circuit shown in figure 19 provides the nec es - sary level-shifting required in a single-supply system. in this case, avdd, which is the positive analog supply for both the ad9761 and the op amp, is also used to level-shift the differ - ential output of the ad9761 to midsupply (i.e., avdd/2) . c opt 200 1k iouta ioutb ad9761 r load 50 200 ad8042 500 r load 50 1k avdd figure 19. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 20 shows the ad9761 confgured to provide a uni - polar output range of approximately 0 v to 0.5 v since the nominal full-scale current, i outfs , of 10 ma fows through an r load of 50 . in the case of a doubly terminated low-pass flter, r load represents the equivalent load resistance seen by iouta or ioutb. the unused output (iouta or ioutb) can be connected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as the positive compliance range is adhered to. 50 iouta ioutb ad9761 50 i outfs = 10m a v out = 0v to 0.5v figure 20. 0 v to 0.5 v unbuffered voltage output differential, dc-coupled output confguration with level shifting some applications may require the ad9761 differential outputs to interface to a single-supply quadrature upconverter. although most of these devices provide differential inputs, its common-mode voltage range does not typically extend to ground. as a result, the ground-referenced output sig nals shown in figure 20 must be level shifted to within the specifed common-mode range of the single-supply quadra ture upconverter. figure 21 shows the addition of a resistor pull- up network that provides the level shifting function. the use of matched resistor networks will maintain maximum gain matching and minimum offset performance between the i and q channels. note, the resistor pull-up network will introduce approximately 6 db of signal attenuation. 50 ** iouta ioutb ad9761 50 ** 500 * 500 * 500 * 500 * avdd v in+ v inC quadrature upconverter *ohmtek to mc-1603-5000d ** ohmtek to mc-1603-1000d figure 21. differential, dc-coupled output confguration with level-shifting power and grounding considerations in systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. proper rf techniques must be used in device selection, placement and routing, and supply bypass ing and grounding. the evaluation board for the ad9761, which uses a 4-layer pc board, serves as a good example for the previously mentioned considerations. the evaluation board provides an illustration of the recommended printed circuit board ground, power, and signal plane layout. proper grounding and decoupling should be a primary objec - tive in any high speed, high resolution system. the ad9761 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physically possible. similarly, dvdd, the digital supply should be decoupled as close to dcom as physically as possible. for those applications requiring a single 5 v or 3.3 v supply for both the analog and digital supply, a clean analog sup ply may be generated using the circuit shown in figure 22. the circuit consists of a differential lc flter with separate power supply and return lines. lower noise can be attained using low esr type electrolytic and tantalum capacitors. 0.1 f cer. 10 f C22 f t ant . 100 f elect. avdd acom + + C C ferrit e beads 5v or 3v powe r supply ttl/cmo s l ogic circuit s figure 22. differential lc filter for single 5 v or 3 v applications rev. c rev. c
ad9761 C1 6 C ad9761 C1 7 C maintaining low noise on power supplies and ground is critical to obtaining optimum results from the ad9761. if properly implemented, ground planes can perform a host of func tions on high speed circuit boards such as bypassing, shielding, current transport. in mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confned to the areas cover ing the analog signal traces and the digital ground plane con fned to areas covering the digital interconnects. all analog ground pins of the dac, reference, and other analog components should be tied directly to the analog ground plane. the two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath, or within 1/2 inch of the dac to maintain optimum performance. care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. on the digital side, this includes the digital input lines running to the dac as well as any clock signals. on the analog side, this includes the dac output signal, reference signal, and the supply feeders. the use of wide runs or planes in the routing of power lines is also recommended. this serves the dual role of provid ing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropri - ate ground plane. it is essential that care be taken in the layout of signal and power ground interconnects to avoid induc ing extraneous voltage drops in the signal ground paths. it is recommended that all connections be short, di rect, and as physically close to the package as possible in order to minimize the sharing of conduction paths between dif fer - ent currents. when runs exceed an inch in length, strip line techniques with a proper termination resistor should be considered. the necessity and value of this resistor will be dependent upon the logic family used. for a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to analog devices application notes an-280 and an-333. applications using the ad9761 for qam modulation qam is one of the most widely used digital modulation schemes in digital communication systems. this modula tion technique can be found in both fdm as well as spread spectrum (i.e., cdma) based systems. a qam signal is a carrier frequency that is modulated both in amplitude (i.e., am modulation) and in phase (i.e., pm modulation). it can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. this re sults in an in-phase (i) carrier component and a quadrature (q) carrier component at a 90 phase shift with respect to the i component. the i and q components are then summed to provide a qam signal at the specifed carrier frequency. a common and traditional implementation of a qam modulator is shown in figure 23. the modulation is per formed in the analog domain in which two dacs are used to gen - erate the baseband i and q components, respectively. each component is then typically applied to a nyquist flter before being applied to a quadrature mixer. the matching nyquist flter shapes and limits each components spectral enve lope while minimizing intersymbol interference. the dac is typically updated at the qam symbol rate or pos sibly a multiple of it if an interpolating flter precedes the dac. the use of an interpolating flter typically eases the imple - mentation and complexity of the analog flter, which can be a signifcant contributor to mismatches in gain and phase between the two baseband channels. a quadrature mixer modulates the i and q components with in-phase and quadrature phase carrier frequency and then sums the two outputs to provide the qam signal. s 0 90 carrier freq nyquist filters quadrature modulator to mixer iout qout ad9761 10 dsp or asic figure 23. typical analog qam architecture evaluation board the ad9761-eb is an evaluation board for the ad9761 dual 10-bit, 40 msps dac. careful attention to layout and circuit design along with prototyping area allows the user to easily and effectively evaluate the ad9761. this board allows the user the fexibility to operate each of the ad9761 dacs in a single-ended or differential output confguration. each of the dacs single-ended outputs are terminated in a 50 resistor. evaluation using a transform er coupled output can be accomplished simply by installing a mini-circuits transformer (i.e., model t2-1t) into the available socket. the digital inputs are designed to be driven directly from various word generators with the on-board option to add a resistor network for proper load termination. separate 50 terminated sma connectors are also provided for the clock, write, and select inputs. provisions are also made to operate the ad9761 with either the internal or an external reference as well as to exercise the power-down feature. rev. c rev. c
ad9761 C1 8 C ad9761 C1 9 C figure 24a. evaluation board schematic rev. c rev. c
ad9761 C1 8 C ad9761 C1 9 C figure 24b. evaluation board schematic rev. c rev. c
ad9761 C2 0 C ad9761 C2 1 C figure 25. silkscreen layertop figure 26. component side pcb layout (layer 1) rev. c rev. c
ad9761 C2 0 C ad9761 C2 1 C figure 27. ground plane pcb layout (layer 2) figure 28. power plane pcb layout (layer 3) rev. c rev. c
ad9761 C2 2 C ad9761 C2 3 C figure 29. solder side pcb layout (layer 4) figure 30. silkscreen layerbottom rev. c rev. c
ad9761 C2 2 C ad9761 C2 3 C outline dimensions 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters 0.25 0.09 0.95 0.75 0.55 8 4 0 0.05 mi n 1.85 1.75 1.65 2.00 ma x 0.38 0.22 seating plane 0.65 bs c 0.10 coplanarit y 28 15 14 1 10.50 10.20 9.90 5.60 5.30 5.00 8.20 7.80 7.40 compliant to jedec standards mo-150ah rev. c rev. c
c00615C0C6/03(c) C2 4 C ad9761 revision history location page 6/03data sheet changed from rev. b to rev. c. renumbered tpcs and subsequent fgures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 rev. c

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